View CM6900IP_243320.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CM6900
PFC/PWM COMBO w/ INRUSH CURRENT CONTROL & SEPARATED PFCOVP GENERAL DESCRIPTION
The CM6900 is a controller for power factor corrected, switched mode power suppliers. Power Factor Correction (PFC) allows the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching FETs, and results in a power supply that fully compiles with IEC-1000-3-2 specifications. Intended as a BiCMOS version of the industry-standard ML4824, CM6900 includes circuits for the implementation of leading edge, average current, "boost" type power factor correction and a trailing edge, pulse width modulator (PWM). The CM6900 has additional features besides all the features of CM6800. Additional features are Inrush Current Control, Separated PFC OVP pin, Separated Power VCCA pin and Analog VCCA pin, and Separated Power Ground pin and Analog Ground pin. Gate-driver with 1A capabilities minimizes the need for external driver circuits. Low power requirements improve efficiency and reduce component costs. An over-voltage comparator shuts down the PFC section in the event of a sudden decrease in load. The PFC section also includes peak current limiting and input voltage brownout protection. The PWM section can be operated in current or voltage mode, at up to 250kHz, and includes an accurate 50% duty cycle limit to prevent transformer saturation. ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !
FEATURES
! Patent Filed #5,565,761, #5,747,977, #5,742,151, #5,804,950, #5,798,635 Inrush Current Control Separated PFC OVP pin Separated Power VCCA and Analog VCCA Separated Power Ground and Analog Ground Additional folded-back current limit for PWM section. 23V Bi-CMOS process VIN OK guaranteed turn on PWM at 2.5V instead of 1.5V Internally synchronized leading edge PFC and trailing edge PWM in one IC Slew rate enhanced transconductance error amplifier for ultra-fast PFC response Low start-up current (100A typ.) Low operating current (3.0mA type.) Low total harmonic distortion, high PF Reduces ripple current in the storage capacitor between the PFC and PWM sections Average current, continuous or discontinuous boost leading edge PFC VCCA OVP Comparator Low Power Detect Comparator PWM configurable for current mode or voltage mode operation Current fed gain modulator for improved noise immunity Brown-out control, over-voltage protection, UVLO, and soft start, and Reference OK
24 Hours Technical Support---WebSIM
Champion provides customers an online circuit simulation tool called WebSIM. You could simply logon our website at www.champion-micro.com for details.
2003/04/23 Preliminary Rev. 1.2
Champion Microelectronic Corporation
Page 1
CM6900
PFC/PWM COMBO w/ INRUSH CURRENT CONTROL & SEPARATED PFCOVP APPLICATIONS
! ! ! ! ! ! ! ! ! Desktop PC Power Supply Internet Server Power Supply IPC Power Supply UPS Battery Charger DC Motor Power Supply Monitor Power Supply Telecom System Power Supply Distributed Power
1 2 3 4 5 6 7 8 9 10 IEAO IAC ISENSE VRMS
INRUSHSTOP B
PIN CONFIGURATION
SOP-20 (S20) / PDIP-20 (P20) Top View
VEAO VFB VFB2 VREF VCCA VDDD P FC O U T PW M O U T VSSD AG N D 20 19 18 17 16 15 14 13 12 11
SS VDC RAM P1 RAM P2 D C ILIMIT
PIN DESCRIPTION
Pin No.
1 2 3 4 5
Symbol
IEAO IAC ISENSE VRMS PB
Description
PFC transconductance current error amplifier output PFC gain control reference input Current sense input to the PFC current limit comparator Input for PFC RMS line voltage compensation or during the start-up condition and it is VCCA when Inrush condition has been removed. Connection point for the PWM soft start capacitor PWM voltage feedback input Oscillator timing node; timing set by RT CT
Min.
0 0 -5 0 0
Operating Voltage Typ. Max. Unit
4.25 1 0.7 6 VCCA V mA V V V
INRUSHSTO Inrush Current Control pin, It is low when Inrush current is high
6 7 8
SS VDC RAMP 1 (RTCT)
0 0 1.2
VREF+0.7 VREF+0.7 3.9
V V V
9
RAMP 2
When in current mode, this pin functions as the current sense input; when in voltage mode, it is the PWM input from PFC (PWM RAMP) output (feed forward ramp). PWM current limit comparator input Analog Ground Digital Ground PWM driver output PFC driver output
0
VREF+0.7
V
10 11 12 13 14
DC ILIMIT AGND VSSD PWM OUT PFC OUT
0
1
V
0 0
VDDD VDDD
V V
2003/04/23 Preliminary Rev. 1.2
Champion Microelectronic Corporation
Page 2
CM6900
PFC/PWM COMBO w/ INRUSH CURRENT CONTROL & SEPARATED PFCOVP
15 VDDD Digital Power VCCA0.3 16 17 18 19 20 VCCA VREF VFB2 VFB VEAO Analog Power Buffered output for the internal 7.5V reference PFC transconductance voltage error amplifier input PFC transconductance voltage error amplifier input PFC transconductance voltage error amplifier output 0 0 0 10 15 7.5 2.5 2.5 3 3 6 VCCA VCCA+0. 3 20 V V V V V
SIMPLIFIED BLOCK DIAGRAM
20 VEAO IEAO 1 18 VFB2 16 VCCA
VCCA LOW POWER DETECT 3.5K
+ . +
VCC OVP
+ +
PFC OVP
.
7.5V REFERENCE
VREF 17
19
VFB
-
GMV
.
2.5V 2 4 ISENSE INRUSHSTOPB 5 8 RAMP1 IAC VRMS
+ -
GAIN MODULATOR 3.5K Inrush Current
3
+ -
UVLO 350
-1.8V
9
RAMP2
SW SPST
7
VDC
VCCA
-
20uA 350 SS
SW SPST SW SPST SW SPST
VIN OK
VREF
Q S
10
DC ILIMIT
R
2003/04/23 Preliminary Rev. 1.2
Champion Microelectronic Corporation
+
6
2.45V
+
-
+
+
1.5V
-
+
0.5V
-
19.4V
2.75V GMI PFC CMP
-
S
Q
VDDD
MPPFC
15
R
Q
-1V
+ S Q
PFC OUT 14
PFC ILIMIT
R Q MNPFC
VSSD
OSCILLATOR
DUTY CYCLE LIMIT
PWM DUTY
CLK PFCOUT
PWM CMP
PWMOUT
S Q
VDDD
MPPWM
PWM OUT SS CMP VFB
.
13
R
Q MNPWM
1.0V
DC ILIMIT
VSSD 12
VCCA
UVLO CM6900(ON:13V/OFF:10V)
AGND 11
Page 3
CM6900
PFC/PWM COMBO w/ INRUSH CURRENT CONTROL & SEPARATED PFCOVP ORDERING INFORMATION
Part Number CM6900IP CM6900IS Temperature Range -40 to 125 -40 to 125 Package 20-Pin PDIP (P20) 20-Pin Wide SOP (S20)
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum ratings are those values beyond which the device could be permanently damaged.
Parameter
VCCA and PVDD IEAO ISENSE Voltage PFC OUT PWMOUT INRUSHSTOPB Voltage on Any Other Pin IREF IAC Input Current Peak PFC OUT Current, Source or Sink Peak PWM OUT Current, Source or Sink PFC OUT, PWM OUT Energy Per Cycle Junction Temperature Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Thermal Resistance (JA) Plastic DIP Plastic SOIC
Min.
0 -5 GND - 0.3 GND - 0.3 GND - 0.3 GND - 0.3
Max.
23 4.5 0.7 VCCA + 0.3 VCCA + 0.3 VCCA + 0.3 VREF + 0.3 10 1 1 1 1.5 150 150 125 260 80 105
Units
V V V V V V V mA mA A A J /W /W
-65 -40
ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply VCCA=+15V,
RT = 52.3k, CT = 470pF, TA=Operating Temperature Range (Note 1) CM6900 Min. 0 VNONINV = VINV, VEAO = 3.75V Note 2 30 2.45 -1.0 5.8 VFB = 3V, VEAO = 6V VFB = 1.5V, VEAO = 1.5V 11V < VCCA < 16.5V 30 50 50 65 2.5 -0.5 6.0 0.1 -35 40 60 60 0.4 -20 Typ. Max. 5 90 2.55
Symbol
Parameter
Test Conditions Voltage Error Amplifier (gmv)
Unit
Input Voltage Range Transconductance Feedback Reference Voltage Input Bias Current Output High Voltage Output Low Voltage Sink Current Source Current Open Loop Gain Power Supply Rejection Ratio
V mho V A V V A A dB dB
2003/04/23 Preliminary Rev. 1.2
Champion Microelectronic Corporation
Page 4
CM6900
PFC/PWM COMBO w/ INRUSH CURRENT CONTROL & SEPARATED PFCOVP ELECTRICAL CHARACTERISTICS (Conti.) Unless otherwise stated, these specifications apply VCCA=+15V, RT = 52.3k, CT = 470pF, TA=Operating Temperature Range (Note 1)
Symbol Parameter Test Conditions Current Error Amplifier (gmi) Input Voltage Range Transconductance Input Offset Voltage Input Bias Current Output High Voltage Output Low Voltage Sink Current Source Current Open Loop Gain Power Supply Rejection Ratio Threshold Voltage Hysteresis Low Power Detect Comparator Threshold Voltage VCCA OVP Comparator Threshold Voltage Hysteresis PFC ILIMIT Comparator Threshold Voltage (PFC ILIMIT VTH - Gain Modulator Output) Delay to Output (Note 4) Threshold Voltage Delay to Output (Note 4) Threshold Voltage Hysteresis GAIN Modulator IAC = 100A, VRMS = VFB = 1V Gain (Note 3) IAC = 100A, VRMS = 1.1V, VFB = 1V IAC = 150A, VRMS = 1.8V, VFB = 1V IAC = 300A, VRMS = 3.3V, VFB = 1V Bandwidth Output Voltage = 3.5K*(ISENSE-IOFFSET) Initial Accuracy Voltage Stability Temperature Stability IAC = 100A IAC = 250A, VRMS = 1.1V, VFB = 1V Oscillator TA = 25 11V < VCCA < 16.5V 0.70 0.59 1.47 0.66 0.21 10 0.80 0.90 0.81 2.03 0.92 0.29 MHz V Overdrive Voltage = 100mV VIN OK Comparator 2.35 0.8 2.45 1.0 2.55 1.2 V V Overdrive Voltage = -100mV DC ILIMIT Comparator 0.95 1.0 250 1.05 V ns -1.10 80 -1.00 200 250 -0.90 V mV ns 19 1.40 19.4 1.5 20 1.65 V V 0.4 0.5 0.6 V 11V < VCCA < 16.5V PFC OVP Comparator 2.70 230 2.77 2.85 290 V mV ISENSE = +0.5V, IEAO = 4.0V ISENSE = -0.5V, IEAO = 1.5V 35 60 60 VNONINV = VINV, VEAO = 3.75V -1.5 50 -12 -1.0 4.0 -0.5 4.25 0.65 -65 75 70 75 1.0 -35 100 0.7 150 12 V mho mV A V V A A dB dB CM6900 Min. Typ. Max. Unit
66 1 2
75.5
kHz % %
2003/04/23 Preliminary Rev. 1.2
Champion Microelectronic Corporation
Page 5
CM6900
PFC/PWM COMBO w/ INRUSH CURRENT CONTROL & SEPARATED PFCOVP ELECTRICAL CHARACTERISTICS
(Conti.) Unless otherwise stated, these specifications apply
VCCA=+15V, RT = 52.3k, CT = 470pF, TA=Operating Temperature Range (Note 1) CM6900 Min. 68 2.5 500 VRAMP2 = 0V, VRAMP1 = 2.5V Reference Output Voltage Line Regulation Load Regulation Temperature Stability Total Variation Long Term Stability Minimum Duty Cycle Maximum Duty Cycle Output Low Rdson Line, Load, Temp TJ = 125, 1000HRs PFC VIEAO > 4.0V VIEAO < 1.2V IOUT = -20mA at room temp IOUT = -100mA at room temp IOUT = 10mA, VCCA = 9V at room temp Output High Rdson Rise/Fall Time (Note 4) Duty Cycle Range IOUT = -20mA at room temp Output Low Rdson IOUT = -100mA at room temp IOUT = 10mA, VCCA = 9V Output High Rdson Rise/Fall Time (Note 4) Start-Up Current Operating Current Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis IOUT = 20mA at room temp IOUT = 100mA at room temp CL = 1000pF Supply VCCA = 12V, CL = 0 14V, CL = 0 CM6900 CM6900 12.74 2.85 100 3.0 13 3.0 150 7.0 13.26 3.15 A mA V V 0.4 15 15 50 IOUT = 20mA at room temp IOUT = 100mA at room temp CL = 1000pF PWM 0-45 0-47 0-49.3 15 15 0.8 20 20 % ohm ohm V ohm ohm ns 0.4 15 15 50 90 95 15 15 0.8 20 20 0 % % ohm ohm V ohm ohm ns 7.35 5 TA = 25, I(VREF) = 1mA 11V < VCCA < 16.5V 0mA < I(VREF) < 7mA; TA = 0~70 0mA < I(VREF) < 5mA; TA = -40~85 7.4 7.5 10 10 10 0.4 7.65 25 7.6 25 20 20 V mV mV mV % V mV 6.5 700 10.5 Typ. Max. 84
Symbol
Parameter Total Variation Ramp Valley to Peak Voltage PFC Dead Time (Note 4) CT Discharge Current
Test Conditions Line, Temp
Unit kHz V ns mA
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Note 2: Includes all bias currents to other circuits connected to the VFB pin. Note 3: Gain = K x 5.375V; K = (ISENSE - IOFFSET) x [IAC (VEAO - 0.625)] ; VEAOMAX = 6V Note 4: Guaranteed by design, not 100% production test.
-1
2003/04/23 Preliminary Rev. 1.2
Champion Microelectronic Corporation
Page 6
CM6900
PFC/PWM COMBO w/ INRUSH CURRENT CONTROL & SEPARATED PFCOVP TYPICAL PERFORMANCE CHARACTERISTIC
127 120 Transconductance (umho) 113 106 99 92 85 78 71 64 57 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 VFB (V) 3
Transconductance (umho)
220 200 180 160 140 120 100 80 60 40 20 0
-500 -400 -300 -200 -100 0 100 200 300 400 500
ISENSE (mV)
Voltage Error Amplifier (gmv) Transconductance
Current Error Amplifier (gmi) Transconductance
0.4 Variable Gain Block Constant (K) 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRMS (V) Gain
2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VRMS (V)
Gain Modulator Transfer Characteristic (K)
Gain
K=
-1 IGAINMOD - IOFFSET mV IAC x (6 - 0.625)
Gain =
ISENSE - IOFFSET IAC
2003/04/23 Preliminary Rev. 1.2
Champion Microelectronic Corporation
Page 7
CM6900
PFC/PWM COMBO w/ INRUSH CURRENT CONTROL & SEPARATED PFCOVP
Functional Description
The CM6900 consists of an average current controlled, continuous boost Power Factor Correction (PFC) front end and a synchronized Pulse Width Modulator (PWM) back end. The PWM can be used in either current or voltage mode. In voltage mode, feedforward from the PFC output buss can be used to improve the PWM's line regulation. In either mode, the PWM stage uses conventional trailing edge duty cycle modulation, while the PFC uses leading edge modulation. This patented leading/trailing edge modulation technique results in a higher usable PFC error amplifier bandwidth, and can significantly reduce the size of the PFC DC buss capacitor. The synchronized of the PWM with the PFC simplifies the PWM compensation due to the controlled ripple on the PFC output capacitor (the PWM input capacitor). The PWM section of the CM6900 runs at the same frequency as the PFC. In addition to power factor correction, a number of protection features have been built into the CM6900. These include soft-start, PFC overvoltage protection, peak current limiting, brownout protection, duty cycle limiting, and under-voltage lockout. line voltage. One of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. A commonly used value is 385VDC, to allow for a high line of 270VACrms. The other condition is that the current drawn from the line at any given instant must be proportional to the line voltage. Establishing a suitable voltage control loop for the converter, which in turn drives a current error amplifier and switching output driver satisfies the first of these requirements. The second requirement is met by using the rectified AC line voltage to modulate the output of the voltage control loop. Such modulation causes the current error amplifier to command a power stage current that varies directly with the input voltage. In order to prevent ripple, which will necessarily appear at the output of boost circuit (typically about 10VAC on a 385V DC level), from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low. A final refinement is to adjust the overall gain of the PFC such to be proportional to 1/VIN2, which linearizes the transfer function of the system as the AC input to voltage varies. Since the boost converter topology in the CM6900 PFC is of the current-averaging type, no slope compensation is required.
Power Factor Correction
Power factor correction makes a nonlinear load look like a resistive load to the AC line. For a resistor, the current drawn from the line is in phase with and proportional to the line voltage, so the power factor is unity (one). A common class of nonlinear load is the input of most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. The peak-charging effect, which occurs on the input filter capacitor in these supplies, causes brief high-amplitude pulses of current to flow from the power line, rather than a sinusoidal current in phase with the line voltage. Such supplies present a power factor to the line of less than one (i.e. they cause significant current harmonics of the power line frequency to appear at their input). If the input current drawn by such a supply (or any other nonlinear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the AC line and a unity power factor will be achieved. To hold the input current draw of a device drawing power from the AC line in phase with and proportional to the input voltage, a way must be found to prevent that device from loading the line except in proportion to the instantaneous line voltage. The PFC section of the CM6900 uses a boost-mode DC-DC converter to accomplish this. The input to the converter is the full wave rectified AC line voltage. No bulk filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges (at twice line frequency) from zero volts to the peak value of the AC input and back to zero. By forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current drawn from the power line is proportional to the input
PFC Section
Inrush Current Control This section is an additional function besides CM6800 functions. The INRUSHSTOPB pin is low during inrush current condition. It happens during start-up and high input current when ISENSE is less than -1.8V. Gain Modulator Figure 1 shows a block diagram of the PFC section of the CM6900. The gain modulator is the heart of the PFC, as it is this circuit block which controls the response of the current loop to line voltage waveform and frequency, rms line voltage, and PFC output voltages. There are three inputs to the gain modulator. These are: 1. A current representing the instantaneous input voltage (amplitude and waveshape) to the PFC. The rectified AC input sine wave is converted to a proportional current via a resistor and is then fed into the gain modulator at IAC. Sampling current in this way minimizes ground noise, as is required in high power switching power conversion environments. The gain modulator responds linearly to this current. 2. A voltage proportional to the long-term RMS AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at VRMS. The gain modulator's output is inversely 2 proportional to VRMS (except at unusually low values of VRMS where special gain contouring takes over, to limit power dissipation of the circuit components under heavy brownout conditions). The relationship between VRMS and gain is called K, and is illustrated in the Typical Performance Characteristics. 3. The output of the voltage error amplifier, VEAO. The gain modulator responds linearly to variations in this voltage.
2003/04/23 Preliminary Rev. 1.2
Champion Microelectronic Corporation
Page 8
CM6900
PFC/PWM COMBO w/ INRUSH CURRENT CONTROL & SEPARATED PFCOVP
The output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. This current is applied to the virtual-ground (negative) input of the current error amplifier. In this way the gain modulator forms the reference for the current error loop, and ultimately controls the instantaneous current draw of the PFC form the power line. The general for of the output of the gain modulator is: IGAINMOD = In higher power applications, two current transformers are sometimes used, one to monitor the IF of the boost diode. As stated above, the inverting input of the current error amplifier is a virtual ground. Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC, an increase in positive current from the gain modulator will cause the output stage to increase its duty cycle until the voltage on ISENSE is adequately negative to cancel this increased current. Similarly, if the gain modulator's output decreases, the output duty cycle will decrease, to achieve a less negative voltage on the ISENSE pin. Cycle-By-Cycle Current Limiter and Selecting RS The ISENSE pin, as well as being a part of the current feedback loop, is a direct input to the cycle-by-cycle current limiter for the PFC section. Should the input voltage at this pin ever be more negative than -1V, the output of the PFC will be disabled until the protection flip-flop is reset by the clock pulse at the start of the next PFC power cycle. RS is the sensing resistor of the PFC boost converter. During the steady state, line input current x RS = IGAINMOD x 3.5K. Since the maximum output voltage of the gain modulator is IGAINMOD max x 3.5K= 0.8V during the steady state, RS x line input current will be limited below 0.8V as well. Therefore, to choose RS, we use the following equation: RS =0.7V x Vinpeak/(2x Line Input power) For example, if the minimum input voltage is 80VAC, and the maximum input rms power is 200Watt, RS = (0.7V x 80V x 1.414)/(2 x 200) = 0.197 ohm. Separated PFC Overvoltage Protection In the CM6900, PFC OVP is using VFB2, which is separated from VFB to sense OVP condition. The PFC OVP comparator serves to protect the power circuit from being subjected to excessive voltages if the load should suddenly change. A resistor divider from the high voltage DC output of the PFC is fed to VFB. When the voltage on VFB2 exceeds 2.75V, the PFC output driver is shut down. The PWM section will continue to operate. The OVP comparator has 250mV of hysteresis, and the PFC will not restart until the voltage at VFB drops below 2.50V. The VFB power components and the CM6900 are within their safe operating voltages, but not so low as to interfere with the boost voltage regulation loop. Also, VCCA OVP can be served as a redundant PFCOVP protection. VCCA OVP threshold is 19.4V with 1.5V hysteresis.
IAC x VEAO x 1V VRMS2
(1)
More exactly, the output current of the gain modulator is given by: IGAINMOD = K x (VEAO - 0.625V) x IAC Where K is in units of V
-1
Note that the output current of the gain modulator is limited around 228.47A and the maximum output voltage of the gain modulator is limited to 228.47uA x 3.5K=0.8V. This 0.8V also will determine the maximum input power. However, IGAINMOD cannot be measured directly from ISENSE. ISENSE = IGAINMOD-IOFFSET and IOFFSET can only be measured when VEAO is less than 0.5V and IGAINMOD is 0A. Typical IOFFSET is around 60uA. Selecting RAC for IAC pin IAC pin is the input of the gain modulator. IAC also is a current mirror input and it requires current input. By selecting a proper resistor RAC, it will provide a good sine wave current derived from the line voltage and it also helps program the maximum input power and minimum input line voltage. RAC=Vin peak x 7.9K. For example, if the minimum line voltage is 80VAC, the RAC=80 x 1.414 x 7.9K=894Kohm. Current Error Amplifier, IEAO The current error amplifier's output controls the PFC duty cycle to keep the average current through the boost inductor a linear function of the line voltage. At the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current which results from a negative voltage being impressed upon the ISENSE pin. The negative voltage on ISENSE represents the sum of all currents flowing in the PFC circuit, and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier.
2003/04/23 Preliminary Rev. 1.2
Champion Microelectronic Corporation
Page 9
CM6900
PFC/PWM COMBO w/ INRUSH CURRENT CONTROL & SEPARATED PFCOVP
Figure 1. PFC Section Block Diagram
Error Amplifier Compensation The PWM loading of the PFC can be modeled as a negative resistor; an increase in input voltage to the PWM causes a decrease in the input current. This response dictates the proper compensation of the two transconductance error amplifiers. Figure 2 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. The current loop compensation is returned to VREF to produce a soft-start characteristic on the PFC: as the reference voltage comes up from zero volts, it creates a differentiated voltage on IEAO which prevents the PFC from immediately demanding a full duty cycle on its boost converter. PFC Voltage Loop: There are two major concerns when compensating the voltage loop error amplifier, VEAO; stability and transient response. Optimizing interaction between transient response and stability requires that the error amplifier's open-loop crossover frequency should be 1/2 that of the line frequency, or 23Hz for a 47Hz line (lowest anticipated international power frequency). The gain vs. input voltage of the CM6900's voltage error amplifier, VEAO has a specially shaped non-linearity such that under steady-state operating conditions the transconductance of the error amplifier is at a local minimum. Rapid perturbation in line or load conditions will cause the input to the voltage error amplifier (VFB) to deviate from its 2.5V (nominal) value. If this happens, the transconductance of the voltage error amplifier will increase significantly, as shown in the Typical Performance Characteristics. This raises the gain-bandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with a conventional linear gain characteristics.
The Voltage Loop Gain (S)
VOUT VFB VEAO * * VEAO VOUT VFB PIN * 2.5V * GMV * ZCV 2 VOUTDC * VEAO * S * CDC =
ZCV: Compensation Net Work for the Voltage Loop GMv: Transconductance of VEAO PIN: Average PFC Input Power VOUTDC: PFC Boost Output Voltage; typical designed value is 380V. CDC: PFC Boost Output Capacitor PFC Current Loop: The current amplifier, IEAO compensation is similar to that of the voltage error amplifier, VEAO with exception of the choice of crossover frequency. The crossover frequency of the current amplifier should be at least 10 times that of the voltage amplifier, to prevent interaction with the voltage loop. It should also be limited to less than 1/6th that of the switching frequency, e.g. 16.7kHz for a 100kHz switching frequency. The Current Loop Gain (S)
VISENSE DOFF IEAO * * DOFF IEAO ISENSE VOUTDC * RS * GMI * ZCI S * L * 2.5V =
2003/04/23 Preliminary Rev. 1.2
Champion Microelectronic Corporation
Page 10
CM6900
PFC/PWM COMBO w/ INRUSH CURRENT CONTROL & SEPARATED PFCOVP
ISENSE Filter, the RC filter between RS and ISENSE : ZCI: Compensation Net Work for the Current Loop GMI: Transconductance of IEAO VOUTDC: PFC Boost Output Voltage; typical designed value is 380V and we use the worst condition to calculate the ZCI RS: The Sensing Resistor of the Boost Converter 2.5V: The Amplitude of the PFC Leading Modulation Ramp L: The Boost Inductor There is a modest degree of gain contouring applied to the transfer characteristic of the current error amplifier, to increase its speed of response to current-loop perturbations. However, the boost inductor will usually be the dominant factor in overall current loop response. Therefore, this contouring is significantly less marked than that of the voltage error amplifier. This is illustrated in the Typical Performance Characteristics. There are 2 purposes to add a filter at ISENSE pin: 1.) Protection: During start up or inrush current conditions, it will have a large voltage cross Rs which is the sensing resistor of the PFC boost converter. It requires the ISENSE Filter to attenuate the energy. 2.) To reduce L, the Boost Inductor: The ISENSE Filter also can reduce the Boost Inductor value since the ISENSE Filter behaves like an integrator before going ISENSE which is the input of the current error amplifier, IEAO. The ISENSE Filter is a RC filter. The resistor value of the ISENSE Filter is between 100 ohm and 50 ohm because IOFFSET x the resistor can generate an offset voltage of IEAO. By selecting RFILTER equal to 50 ohm will keep the offset of the IEAO less than 5mV. Usually, we design the pole of ISENSE Filter at fpfc/6, one sixth of the PFC switching frequency. Therefore, the boost inductor can be reduced 6 times without disturbing the stability. Therefore, the capacitor of the ISENSE Filter, CFILTER, will be around 283nF.
2003/04/23 Preliminary Rev. 1.2
Champion Microelectronic Corporation
Page 11
CM6900
PFC/PWM COMBO w/ INRUSH CURRENT CONTROL & SEPARATED PFCOVP
Oscillator (RAMP1)
The oscillator frequency is determined by the values of RT and CT, which determine the ramp and off-time of the oscillator output clock: fOSC = of the current flowing in the converter's output stage. DCILIMIT, which provides cycle-by-cycle current limiting, is typically connected to RAMP2 in such applications. For voltage-mode, operation or certain specialized applications, RAMP2 can be connected to a separate RC timing network to generate a voltage ramp against which VDC will be compared. Under these conditions, the use of voltage feedforward from the PFC buss can assist in line regulation accuracy and response. As in current mode operation, the DC ILIMIT input is used for output stage overcurrent protection. No voltage error amplifier is included in the PWM stage of the CM6900, as this function is generally performed on the output side of the PWM's isolation boundary. To facilitate the design of optocoupler feedback circuitry, an offset has been built into the PWM's RAMP2 input which allows VDC to command a zero percent duty cycle for input voltages below 1.25V. PWM Current Limit The DC ILIMIT pin is a direct input to the cycle-by-cycle current limiter for the PWM section. Should the input voltage at this pin ever exceed 1V, the output flip-flop is reset by the clock pulse at the start of the next PWM power cycle. Beside, the cycle-by-cycle current, when the DC ILIMIT triggered the cycle-by-cycle current, it also softly discharge the voltage of soft start capacitor. It will limit PWM duty cycle mode. Therefore, the power dissipation will be reduced during the dead short condition. VIN OK Comparator The VIN OK comparator monitors the DC output of the PFC and inhibits the PWM if this voltage on VFB is less than its nominal 2.45V. Once this voltage reaches 2.45V, which corresponds to the PFC output capacitor being charged to its rated boost voltage, the soft-start begins. PWM Control (RAMP2) When the PWM section is used in current mode, RAMP2 is generally used as the sampling point for a voltage representing the current un the primary of the PWM's output transformer, derived either by a current sensing resistor or a current transformer. In voltage mode, it is the input for a ramp voltage generated by a second set of timing components (RRAMP2, CRAMP2),that will have a minimum value of zero volts and should have a peak value of approximately 5V. In voltage mode operation, feedforward from the PFC output buss is an excellent way to derive the timing ramp for the PWM stage. Soft Start Start-up of the PWM is controlled by the selection of the external capacitor at SS. A current source of 20A supplies the charging current for the capacitor, and start-up of the PWM begins at 1.25V. Start-up delay can be programmed by the following equation: CSS = tDELAY x
1 tRAMP + tDEADTIME
The dead time of the oscillator is derived from the following equation: tRAMP = CT x RT x In VREF - 1.25 VREF - 3.75 at VREF = 7.5V: tRAMP = CT x RT x 0.51 The dead time of the oscillator may be determined using: tDEADTIME =
2.5V x CT = 450 x CT 5.5mA
The dead time is so small (tRAMP >> tDEADTIME ) that the operating frequency can typically be approximately by: fOSC =
1 tRAMP
EXAMPLE: For the application circuit shown in the datasheet, with the oscillator running at: fOSC = 100kHz =
1 tRAMP
-5
Solving for CT x RT yields 1.96 x 10 . Selecting standard components values, CT = 390pF, and RT = 51.1k The dead time of the oscillator adds to the Maximum PWM Duty Cycle (it is an input to the Duty Cycle Limiter). With zero oscillator dead time, the Maximum PWM Duty Cycle is typically 45%. In many applications, care should be taken that CT not be made so large as to extend the Maximum Duty Cycle beyond 50%. This can be accomplished by using a stable 390pF capacitor for CT.
PWM Section
Pulse Width Modulator The PWM section of the CM6900 is straightforward, but there are several points which should be noted. Foremost among these is its inherent synchronization to the PFC section of the device, from which it also derives its basic timing. The PWM is capable of current-mode or voltage-mode operation. In current-mode applications, the PWM ramp (RAMP2) is usually derived directly from a current sensing resistor or current transformer in the primary of the output stage, and is thereby representative
20A 1.25V
2003/04/23 Preliminary Rev. 1.2
Champion Microelectronic Corporation
Page 12
CM6900
PFC/PWM COMBO w/ INRUSH CURRENT CONTROL & SEPARATED PFCOVP
where CSS is the required soft start capacitance, and the tDEALY is the desired start-up delay. It is important that the time constant of the PWM soft-start allow the PFC time to generate sufficient output power for the PWM section. The PWM start-up delay should be at least 5ms. Solving for the minimum value of CSS: CSS = 5ms x The ratio of winding transformer for the bootstrap should be set between 18V and 15V. A filter network is recommended between VCCA (pin 16) and bootstrap winding. The resistor of the filter can be set as following. RFILTER x IVCCA ~ 2V, IVCCA = IOP + (QPFCFET + QPWMFET ) x fsw IOP = 3mA (typ.) If anything goes wrong, and VCCA goes beyond 19.4V, the PFC gate (pin 14) drive goes low and the PWM gate drive (pin 13) remains function. The resistor's value must be chosen to meet the operating current requirement of the CM6900 itself (5mA, max.) plus the current required by the two gate driver outputs. EXAMPLE: With a wanting voltage called, VBIAS ,of 18V, a VCCA of 15V and the CM6900 driving a total gate charge of 90nC at 100kHz (e.g. 1 IRF840 MOSFET and 2 IRF820 MOSFET), the gate driver current required is: IGATEDRIVE = 100kHz x 90nC = 9mA RBIAS =
20A = 80nF 1.25V
Caution should be exercised when using this minimum soft start capacitance value because premature charging of the SS capacitor and activation of the PWM section can result if VFB is in the hysteresis band of the VIN OK comparator at start-up. The magnitude of VFB at start-up is related both to line voltage and nominal PFC output voltage. Typically, a 1.0F soft start capacitor will allow time for VFB and PFC out to reach their nominal values prior to activation of the PWM section at line voltages between 90Vrms and 265Vrms. Generating VCCA After turning on CM6900 at 13V, the operating voltage can vary from 10V to 19.4V. The threshold voltage of VCCA OVP comparator is 19.4V. The hysteresis of VCCA OVP is 1.5V. When VCCA see 19.4V, PFCOUT will be low, and PWM section will not be disturbed. That's the two ways to generate VCCA. One way is to use auxiliary power supply around 15V, and the other way is to use bootstrap winding to self-bias CM6900 system. The bootstrap winding can be either taped from PFC boost choke or from the transformer of the DC to DC stage.
VBIAS - VCC ICC + IG
18V - 15V 5mA + 9mA
RBIAS =
Choose RBIAS = 214 The CM6900 should be locally bypassed with a 1.0F ceramic capacitor. In most applications, an electrolytic capacitor of between 47F and 220F is also required across the part, both for filtering and as part of the start-up bootstrap circuitry.
2003/04/23 Preliminary Rev. 1.2
Champion Microelectronic Corporation
Page 13
CM6900
PFC/PWM COMBO w/ INRUSH CURRENT CONTROL & SEPARATED PFCOVP
Leading/Trailing Modulation
Conventional Pulse Width Modulation (PWM) techniques employ trailing edge modulation in which the switch will turn on right after the trailing edge of the system clock. The error amplifier output is then compared with the modulating ramp up. The effective duty cycle of the trailing edge modulation is determined during the ON time of the switch. Figure 4 shows a typical trailing edge control scheme. In case of leading edge modulation, the switch is turned OFF right at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned ON. The effective duty-cycle of the leading edge modulation is determined during OFF time of the switch. Figure 5 shows a leading edge control scheme. One of the advantages of this control technique is that it required only one system clock. Switch 1(SW1) turns off and switch 2 (SW2) turns on at the same instant to minimize the momentary "no-load" period, thus lowering ripple voltage generated by the switching action. With such synchronized switching, the ripple voltage of the first stage is reduced. Calculation and evaluation have shown that the 120Hz component of the PFC's output ripple voltage can be reduced by as much as 30% using this method.
2003/04/23 Preliminary Rev. 1.2
Champion Microelectronic Corporation
Page 14
CM6900
PFC/PWM COMBO w/ INRUSH CURRENT CONTROL & SEPARATED PFCOVP APPLICATION CIRCUIT (CURRENT MODE)
+12V OUT C33
R32
Q4
R18
Inrush R22 R25
C22 C21 +12V C24 R24 R23 R26 C23
U3
U2 L2
D11B
T2B D11A
R16 T2C TP1 C10
+382V
T2A
R13 D6
D5 Q5 RAMP2 R9 R20B R20A REF Q2 Q3 D4 R11 C9 C8 C14
C13 C16 C15 D10
R30
D7 R14
R19
C17
R17 C25 T1B
C20
R15
T1A
VCC
R10
C32 R31A R31B R31
R6
C31 R8
R7A
R7B
20
19
18
17
16
15
14 PFC-OUT
13 RAMP1 PWM-OUT
12
VEAO
CM6900/01/24 U6
I-SENSE VFB2
D2
C4 C12 D1 Q1 D9 R28 C7
RAMP2
VRMS
R12
10
1
2
3
4
5
6
7
8
9
ILIMIT
IEAO
VDC
INR
IAC
SS
AGND
VREF
VCC
C6
VDD
VFB
VSS
D3
11
C5
+12V Return
C11
L1 R27
R21 C30 C18 INRUSH VDC C19 R1B
D8
R1A
R2A
R2B
R3 R4 D14
C2
C3 + D12 D13 C25
R5E
-
R5D C1 R5C R5B VIN R5A AC
2003/04/23 Preliminary Rev. 1.2
Champion Microelectronic Corporation
Page 15
CM6900
PFC/PWM COMBO w/ INRUSH CURRENT CONTROL & SEPARATED PFCOVP APPLICATION CIRCUIT (VOLTAGE MODE)
R5 IVIN_EMC L2
EMC FILTER
L3
R3 RT1 IVIN IVIN IAC D4 PFC_VIN PFC_VIN IBOOT Q1 Q2 R26 18k C23 470p R17A C55A VFB C55A R65A R65A INRUSH INRUSH D10 MUR1100 R17A C10 Q12 R6 R16A IL1 L1 D5
D5 R16A
PFC_Vout IC10
PFC_Vout
VIN AC
R2
C3
C8
R1
C2
R10
R12
R14
C33 100n
Q1 Q2N2222 Q2 Q2N2904
D12
PFC_DC
R22 22 R24
1N4148 R11 R18 R13 R15 R23 75 R25 10k
22
D6 1N4002
D7 C41 1N4002 R64 R59 C30 R58 IEAO 1 2 ISENSE R60 C46 INRUSH SS C47 C44 C45 R56 R57 VCC C48 C49 VREF VDC 5 6 7 8 9 10 VRMS 3 4 IEAO IAC I-SENSE VRMS INR SS VDC VEAO VFB VFB2 VREF VCC VDD PFC-OUT 20 19 18 17 16 15 14 13 12 11 PWM_OUT C56 VREF VCC C52 1u C53 100n R63 C57 VCC VREF C54 C43 R66 100 VEAO
VFB2
RAMP1 PWM-OUT RAMP2 ILIMIT VSS AGND
R62
CM6900/01/24
C50
ILIMIT
R61 470 C51
ILIMIT
R44 C4
ISO1 VDC
PFC_Vout C7 10n
PWM_IN R27 100k C22 10n
C14
R34 C38 4.7 IL4 L4 L5 IC17 IC18 C18 C19 PWM_Rload 500m PWM_Vout C39 ILOAD R45 U1 CM431 R48
10n D9A
R49 R46 C40 R43
D8 D13 MUR1100 MUR1100 T1 D9B
R35 4.7 C22 10n
C17
C15 10n VCC IBIAS C34 100n Q6 Q2N2222 PWM_DC PFC_OUT Q7 Q2N2904 D16 1N4148 R28 T 2:3 22 R29 10k ILIMIT R31 ZD1 6.8V Q3 R32A C31 R33 R32 VCC
2003/04/23 Preliminary Rev. 1.2
Champion Microelectronic Corporation
Page 16
CM6900
PFC/PWM COMBO w/ INRUSH CURRENT CONTROL & SEPARATED PFCOVP PACKAGE DIMENSION
20-PIN PDIP (P20)
PIN 1 ID
20-PIN SOP (P20), 0.300" Wide
PIN 1 ID
2003/04/23 Preliminary Rev. 1.2
Champion Microelectronic Corporation
Page 17
CERAMIC/SURGE ABSORBER SHANGHAI,CHINA
DIODES LAB HANGZHOU,CHINA
CERAMIC/PZT SHINCHU,TAIWAN
DC POWER LAB TAIPEI,TAIWAN
WWW..COM
Copyright (c) Each Manufacturing Company. All Datasheets cannot be modified without permission.
This datasheet has been download from : www..com
100% Free DataSheet Search Site. Free Download. No Register. Fast Search System. www..com

▲Up To Search▲

Price & Availability of CM6900IP

	To Download CM6900IP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .